The 'test model-checking' approach to the verification of formal memory models of multiprocessors

technical reportWe offer a solution to the problem of verifying formal memory models of processors by com bining the strengths of model checking and a formal testing procedure for parallel machines We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated Our experimen tal results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to e??ectively debug design models during early stages of their developmen

A partial order reduction algorithm without the Proviso

Journal ArticleThis paper presents a partial order reduction algorithm, called Two phase, that preserves stutter free LTL properties. Two phase dramatically reduces the number of states visited compared to previous partial order reduction algorithms on most practical protocols. The reason can be traced to a step of the previous algorithms, called the proviso step, that specifies a condition on how a state that closes a loop is expanded. Two phase can be easily combined with an on-the-fly model-checking algorithm to reduce the memory requirements further. Furthermore a simple but powerful selective-caching scheme can also be added to Two phase. Two phase has been implemented in a model-checker called PV (Protocol Verifier) and is in routine use on large problems

Performance studies of PV: an On-the-fly model-checker for LTL-X featuring selective caching and partial order reduction

Journal ArticleWe present an enumerative model-checker PV that uses a new partial order reduction algorithm called Twophase. This algorithm does not use the in-stack check to implement the proviso, making the combination of Twophase with on-the-fly LTL-X model-checking based on nested depth-first search, as well as with selective state caching very straightforward. We present a thorough evaluation of PV in terms of several states, memory, search depth, and runtimes. Our very encouraging results, often orders of magnitude better, are objectively explained in this paper. We also explain the different selective state caching methods supported by PV as well as its user interface geared towards verifying cache coherence protocols for conformance against formal memory models, We offer the source code of PV as well as our examples through out webpage

The 'Test model-checking' approach to the verification of formal memory models of multiprocessors

technical reportWe offer a solution to the problem of verifying formal memory models of processors by combining the strengths of model-checking and a formal testing procedure for parallel machines. We characterize the formal basis for abstracting the tests into test automata and associated memory rule safety properties whose violations pinpoint the ordering rule being violated. Our experimental results on Verilog models of a commercial split transaction bus demonstrates the ability of our method to effectively debug design models during early stages of their development